1. Field of the Invention
The present invention relates to a voltage level shift circuit and a semiconductor device using the same. In particular, the present invention relates to a voltage level shift circuit in which the transition rate of an output signal when an input signal changes from one logic level to another logic level and that of the output signal when the input signal changes from the another logic level to the one logic level are made uniform, and a semiconductor device using the same.
2. Description of Related Art
Semiconductor devices such as a DRAM (Dynamic Random Access Memory) are supplied with a power supply potential VDD and a ground potential VSS (<VDD). The potential difference (voltage) between the power supply potential VDD and the ground potential VSS supplied to a semiconductor device is sometimes referred to as an external voltage VDD. The external voltage VDD becomes a first voltage VDDI (VDDI>VSS) in the semiconductor device. A second voltage VPERI is generated from the first voltage VDDI (VDDI>VPERI). Here, the first voltage VDDI refers to a potential difference between a power supply potential VDD and the ground potential VSS. The second voltage VPERI refers to a potential difference between a power supply potential VPERI and the ground potential VSS.
An input signal input to the semiconductor device from outside is converted into a signal in the range of the ground potential VSS to the power supply potential VDDI by an input signal discrimination unit. The signal is then converted into a signal in the range of the ground potential VSS to the power supply potential VPERI. Hereinafter, such a circuit that converts the voltage range of an input signal from VSS to VDDI into VSS to VPERI will be referred to as a “voltage level shift circuit.” In many cases, the voltage conversion of the voltage level shift circuit is performed by making the operating voltage of an inverter on the input side different from that of an inverter. A conventional voltage level shift circuit is described in Japanese Patent Application Laid-Open No. 2000-163960.
In a typical voltage level shift circuit, the inverter on the input side is driven by the first voltage VDDI and the inverter on the output side is driven by the second voltage VPERI. The output of the inverter on the input side, i.e., the input signal to the inverter on the output side is a binary signal that becomes VDDI when the signal is HIGH, and VSS when the signal is LOW. Either one of a PMOS (Positive channel Metal Oxide Semiconductor) transistor and an NMOS (Negative channel Metal Oxide Semiconductor) transistor included in the inverter on the output side turns on depending on the logical value of the input signal.
When the input signal is HIGH (VDDI), the NMOS transistor turns on and the output signal level of the inverter on the output side becomes VSS. When the input signal is LOW (VSS), the PMOS transistor turns on and the signal level of the inverter on the output side becomes VPERI.
Such a voltage level shift circuit has had a problem that the transition rate (speed) of the output signal when the input signal changes from HIGH to LOW is different from that of the output signal when the input signal changes from LOW to HIGH. More specifically, suppose that the gate-source voltage of the PMOS transistor when the transistor is on is VGSP, and the gate-source voltage of the NMOS transistor when the transistor is on is VGSN. If the input signal=VDDI (HIGH), the gate-source voltage VGSN of the NMOS transistor which is on is VDDI−VSS. On the other hand, if the input signal=VSS (LOW), the gate-source voltage VGSP of the PMOS transistor which is on is VSS−VPERI. The two gate-source voltages do not coincide with each other.
In other words, VGSN at which the NMOS transistor turns on due to the input signal=VDDI (HIGH) in an absolute value is greater than that of VGSP at which the PMOS transistor turns ON due to the input signal=VSS (LOW). For example, assuming that VDDI=1.5 (V), VPERI=1.0 (V), and VSS=0.0 (V), the NMOS transistor turns on at VGSN=1.5 (V) and the PMOS transistor turns on at VGSP=−1.0 (V).
The different ON voltages of the PMOS transistor and the NMOS transistor give rise to a difference in the response characteristic of the voltage level shift circuit depending on the logic of the input signal.